Multi-mode standard cell logic and self-startup for battery-indifferent or pure energy harvesting systems

ABSTRACT

A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, a battery-indifferent or pure energy harvesting multi-mode system, a method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, and a method of operating battery-indifferent or pure energy harvesting multi-mode system. The cell gate structure comprises a CMOS gate circuit; a header circuit coupled to the CMOS gate circuit and comprising first and second header transistors for coupling in parallel between a supply voltage and the CMOS gate circuit; and a footer circuit coupled to the CMOS gate circuit and comprising first and second footer transistors for coupling in parallel between the CMOS gate circuit and a ground voltage; wherein the header and footer circuits are configured for switching between different operation modes of the multi-mode system, the different operation modes chosen from a range from a normal mode in which feedback paths from an output of the CMOS gate circuit to the gate of the second header transistor and to the gate of the second footer transistor are substantially or fully disabled for full swing in the output voltage of the CMOS gate circuit, and a leakage suppression mode in which the feedback paths are substantially or fully enabled.

FIELD OF INVENTION

The present invention relates broadly to the field of solid-statecircuits and systems (CMOS), in particular to multi-mode cell logic andself-startup for battery-indifferent or pure energy harvesting systems.

BACKGROUND

Any mention and/or discussion of prior art throughout the specificationshould not be considered, in any way, as an admission that this priorart is well known or forms part of common general knowledge in thefield.

Battery-indifferent systems such as, but no limited to, sensor nodesrequire continuous operation in spite of the intermittently availablebattery energy, and hence require low peak-power operation to fit thefluctuating power made available by the harvester when the battery isout of energy. FIG. 1 shows a chart illustrating thatbattery-indifferent operation of sensor nodes with an integratedharvester need to achieve sub-nW power (minimum power) when the batteryis out of energy, see purely harvested operation mode 100, whilereducing energy when battery-powered (minimum energy) in various batteryoperated modes 101-103. Such harvested power can be very limited (e.g.,nW and below) in aggressively miniaturized systems in the millimeterscale, and is typically well below the leakage consumption of thecircuit being powered.

Recently, purely harvested continuous operation with an on-chipharvester with sub-leakage sub-nW minimum power has been demonstratedfor battery-less operation [1], at the cost of drastically lowerperformance (i.e., clock frequency in the Hz range) and larger energy.On the other hand, conventional miniaturized sensor nodes pursue minimumenergy per operation to maximize the battery lifetime [2-6], but are notable to operate in the sub-leakage regime, and are hence unsuitable forpurely harvested operation.

“Semiconductor device with reduced leakage current and method formanufacture the same” (Cold Brick Semiconductor, Inc., 2013), US20130107651 A1 proposes separate header and footer based approach toreduce leakage in custom standard cells, however there are 8 additionaltransistors required in each standard cell and therefore larger area.

“Ultra-low-power circuit” (Universite Catholique de Louvain (UCL)), U.S.Pat. No. 8,294,492 B2 proposes to integrate one header and one footercontrolling by the output of custom standard cells to reduce leakagecurrent, however the speed of the custom standard cells is heavilydegraded.

Embodiments of the present invention seek to address at least one of theabove problems.

SUMMARY

In accordance with a first aspect of the present invention, there isprovided a cell logic structure for a battery-indifferent or pure energyharvesting multi-mode system, the cell gate structure comprising:

-   -   a CMOS gate circuit;    -   a header circuit coupled to the CMOS gate circuit and comprising        first and second header transistors for coupling in parallel        between a supply voltage and the CMOS gate circuit; and    -   a footer circuit coupled to the CMOS gate circuit and comprising        first and second footer transistors for coupling in parallel        between the CMOS gate circuit and a ground voltage;

wherein the header and footer circuits are configured for switchingbetween different operation modes of the multi-mode system, thedifferent operation modes chosen from a range from a normal mode inwhich feedback paths from an output of the CMOS gate circuit to the gateof the second header transistor and to the gate of the second footertransistor are substantially or fully disabled for full swing in theoutput voltage of the CMOS gate circuit, and a leakage suppression modein which the feedback paths are substantially or fully enabled.

In accordance with a second aspect of the present invention, there isprovided a battery-indifferent or pure energy harvesting multi-modesystem comprising:

-   -   an energy harvesting circuit for generating power for the        multi-mode system;    -   one or more cell logic structures of the first aspect; and    -   a power management circuit for switching between the different        operation modes of the multi-mode system.

In accordance with a third aspect of the present invention, there isprovided a method of operating a cell logic structure for abattery-indifferent or pure energy harvesting multi-mode system, themethod comprising the steps of:

-   -   controlling a header circuit coupled to a CMOS gate circuit, the        header circuit comprising first and second header transistors        for coupling in parallel between a supply voltage and the CMOS        gate circuit, and    -   controlling a footer circuit coupled to the CMOS gate circuit,        the footer circuit comprising first and second footer        transistors for coupling in parallel between the CMOS gate        circuit and a ground voltage;

such that the multi-mode system is switchable between differentoperation modes, the different operation modes chosen from a range froma normal mode in which feedback paths from an output of the CMOS gatecircuit to the gate of the second header transistor and to the gate ofthe second footer transistor are substantially or fully disabled forfull swing in the output voltage of the CMOS gate circuit, and a leakagesuppression mode in which the feedback paths are substantially or fullyenabled.

In accordance with a fourth aspect of the present invention, there isprovided a method of operating a battery-indifferent or pure energyharvesting multi-mode system, comprising the steps of:

-   -   generating power for the multi-mode system using an energy        harvesting circuit;    -   executing the method of the third aspect; and    -   switching between the different operation modes of the        multi-mode system.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will be better understood and readilyapparent to one of ordinary skill in the art from the following writtendescription, by way of example only, and in conjunction with thedrawings, in which:

FIG. 1 illustrates battery-indifferent operation of sensor nodes with anintegrated harvester needing to achieve sub-nW power (minimum power)when the battery is out of energy, while reducing energy whenbattery-powered (minimum energy).

FIG. 2 shows a schematic diagram illustrating a dual-mode systemarchitecture according to an example embodiment, comprisingmicrocontroller and power management, and which can preferably operatein normal (minimum energy) or leakage suppression mode (minimum power)modes.

FIG. 3 shows a circuit diagram illustrating a cell logic structure for abattery-indifferent dual-mode system according to an example embodiment,here a dual-mode inverter and its operation in normal and leakagesuppression mode.

FIG. 4 shows a graph illustrating power/frequency versus tuning voltage(ΔV) in normal mode operation and normal mode operation of the dual-modeinverter of FIG. 3

FIG. 5 shows a graph illustrating measured energy versus V_(DD) (left),a graph illustrating measured frequency versus V_(DD) (middle), and agraph illustrating measured power versus V_(DD) (right) of a dual-mode35-stage ring oscillator according to an example embodiment.

FIG. 6 shows graphs illustrating measured power (top) and energy(bottom) of a microcontroller system according to an example embodimentin LSM (left) and NM (right), when running a program computing themoving average of an input acquired through the GPIO (entire 2 KB memoryis active, T=25° C.).

FIG. 7 shows a block diagram illustrating power management with rippleself-startup consisting of cascaded power gating stages for sequentialactivation of power domains, according to an example embodiment.

FIG. 8 shows graphs illustrating measured current (left) and sequence ofenable signals activating the ripple self-startup stages (right) duringa self-startup according to an example embodiment.

FIG. 9 shows a schematic drawing illustrating a cell logic structure fora battery-indifferent or pure energy harvesting multi-mode system,according to an example embodiment.

FIG. 10 shows a schematic diagram illustrating a battery-indifferent orpure energy harvesting multi-mode system, according to an exampleembodiment.

FIG. 11 shows a flow chart illustrating a method of operating a celllogic structure for a battery-indifferent or pure energy harvestingmulti-mode system, according to an example embodiment.

FIG. 12 shows a flowchart illustrating a method of operatingbattery-indifferent or pure energy harvesting multi-mode system,according to an example embodiment.

DETAILED DESCRIPTION

Embodiments of the present invention provide a novel logic family andself-startup scheme for semiconductor Integrated Chips (ICs), includingbut not limited to standard cell design for digital integrated circuits,based on the concept of dual-mode logic (DML) and ripple power gatingself-startup (RPG). The DML allows digital systems to operate both innormal (NM) and leakage suppression mode (LSM). In NM mode, it allowsthe system to work in a very high energy efficient manner with decentspeed. In LSM mode, the system works with only sub-leakage power (i.e.,below 1 nW) which can operate even without battery. The RPG self-startupscheme enables cold start at reduced harvested power, overcoming theneed for large harvested power peak in [1] at start-up. In exampleembodiments, instead of PMOS headers, NMOS header and PMOS footers areused per cell and can operate at super-cutoff (negative gate overdrive)in sleep mode and can completely cut off the leakage path from supply.

In one embodiment, an example of a microcontroller using DML standardcells and RPG self-startup is presented. The standard cells areconfigured as conventional CMOS gates in NM mode, whereas they areconfigured as dynamic leakage-suppression (DLS) logic [1] in LSM mode,so that their current is pushed below leakage. When the battery orharvested power is sufficient, the system according to an exampleembodiment operates in NM mode with high energy efficiency andperformance. When the battery is out of energy and under limitedharvested power (e.g., solar cell at dim light), the system according toan example embodiment is configured in LSM mode to operate atsub-leakage power. In RPG self-startup, instead of powering up theentire system all at once, the system is partitioned in smaller powerdomains that are sequentially powered by the ripple self-startupaccording to an example embodiment, which progressively turns on therelevant header sleep transistors. A prototype embodiment has beenmanufactured and proven by silicon measurement results.

The described DML and RPG are discussed for microcontrollers, but itwill be appreciated that they are not limited to microcontrollers, butcan be applied to other digital integrated circuits (e.g., digitalsignal processors).

As mentioned above, in one embodiment, the DML and ripple power gatingself-startup was implemented in a typical digital system 200 consistingof a microcontroller (MCU) unit 201 and a power management (PM)sub-system 202, as shown in FIG. 2 . The microcontroller unit 201according to this example embodiment has a processor core 204, 1 KBlatch-based instruction memory (IMEM) 205 and data memory (DMEM) 207(each having four separately power-gated sections e.g. 205 a, 207 a),128B synthesized boot ROM 206, an on-chip clock generator 208, and aGPIO interface 210 for communication with sensors and other peripherals.The MCU unit 201 is designed with a multi-mode, e.g. a dual-mode,standard cell library 209, described in more detail below with referenceto FIG. 3 , which is configured in either NM or LSM mode depending onthe mode signal 211 generated by the power mode configuration block 212,based on the battery 214 condition. It is noted that the term “standardcell” is used because the cells can be used by electronic designautomation (EDA) tools for place and routing. The PM sub-system 202includes a ripple self-startup circuit 216, a DC-DC converter 218, andthe power-mode configuration block 212. The power-mode configurationblock 212 generates the signals to turn on/off the self-startup circuit216, the DC-DC converter 218, and, based on the mode signal 211, thepower gating signals to the cell library 209. When the battery 214 isavailable, the system 200 operates in normal mode with high energyefficiency and performance. When the battery 214 is out of energy andunder limited harvested power (e.g., solar cell 222 at dim light), thesystem 200 is configured in LSM mode to operate at sub-leakage power.Sets of sleep transistors e.g. 224, 226 are provided as part of the MPsub-system 202. Specifically, the lower set of PMOS headers e.g. 224 areused to sequentially turn on power domains in purely harvested mode, aswill be described in more detail below. The top set of PMOS headers e.g.226 are used to turn off any unused power domain in battery powered modeto further reduce the energy consumption, in an example embodiment.

FIG. 3 shows the operation of the proposed dual-mode cells e.g. 300 forthe cell library 209 (FIG. 2 ), where four extra transistors (M1, M2,M5, M6) are added to a conventional CMOS gate 302 (inverter gate, inthis example embodiment). When mode=0 (i.e., NM mode), M1 and M5 areturned on and boosted by ΔV to pull up node n1 to V_(DD) (pull down n2to ground), which disables the feedback paths from transistors M2 andM6, and allows conventional CMOS gate operation, compare NMconfiguration 304.

Voltage boosting by ΔV=0.4V in NM mode was found to be sufficient inthis example embodiment to compensate the threshold voltage drop of M1and M5, and is delivered by the DC-DC converter 218 (FIG. 2 ), which ispowered by the battery 214 (FIG. 2 ) in this mode. In addition, ΔV canbe used as a modulating knob for trading off power for higheroperational frequency and better energy efficiency under a given V_(DD).As shown in FIG. 4 for V_(DD)=0.4V, it can achieve almost 5 orders ofmagnitude tuning in frequency (curve 400) and power (curve 402) bysetting ΔV from V_(DD) to 0.4V. It is noted that embodiments of thepresent invention advantageously have the ability to achieve all/anyintermediate power-performance trade-offs as well. That is, in additionto the two (very far away) design points defining a continuous rangefrom a minimum energy to a minimum power operation mode, embodiments ofthe present invention are able to achieve any intermediate trade-off bytuning ΔV, see FIG. 4 . In that regard, the two design points at minimumenergy and minimum power as described for the dual-mode embodiments areonly by way of example, not limitation. In different embodiments, two ormore design points can be chosen for the different modes of a multi-modesystem from the continuous range of design points, such as illustratedin FIG. 4 . Returning to FIG. 3 , when mode=1 (i.e., LSM mode), M1 andM5 are off (ΔV=−V_(DD)) and the inverter operates as DLS logic [1],compare LSM configuration 306, advantageously assuring minimum(sub-leakage) power thanks to the reverse gate biasing of M1-M6 (i.e.,super-cutoff). More generally, with ΔV>0V, the gate of M1 and M5 isoverdriven to progressively restore full swing in OUT. On the otherhand, with ΔV≤0 V, M1 and M5 are progressively turned OFF to operate asDLS logic [1].

In the measurement of a 35-stage ring oscillator according to an exampleembodiment (FIG. 5 ), LSM mode (curve 500) shows 750× power reduction at0.4V compared to NM mode (curve 502), while NM mode (curve 504) exhibits3,800× speed-up compared to LSM mode (curve 506) and while NM mode(curve 508) shows 5× energy reduction compared to LSM mode (curve 510).Based on this principle, a dual-mode standard cell library 209 (FIG. 2 )is designed according to an example embodiment.

In FIG. 6 , measurements on the dual-mode microcontroller systemaccording to an example embodiment designed with the above describeddual-mode standard cell library and an automated design flow show thatthe minimum-power point in LSM mode occurs at 0.45V and is 595 pW asshown graph 600, which is 198× lower than the minimum power point innormal mode as shown in graph 602. When running a moving averageprogram, the minimum energy point in NM mode is 33 pJ/cycle at 0.45Vwith fully enabled memory banks (14 pJ/cycle when using 512B memory,with other banks being power gated) as shown in graph 604, which is 8.2×(19.4×) lower energy than in LSM mode as shown in graph 606. At the sameminimum energy point, the MCU system according to this exampleembodiment runs at 19 kHz as shown in graph 604, which is 7,755× fasterthan in LSM mode as shown in graph 606. From the results shown in FIG. 6, the dual-mode reconfiguration according to this example embodiment canadvantageously break the tradeoff between minimum-power andminimum-energy encountered in conventional single-mode systems. Comparedto a conventional CMOS design, LSM mode of the dual-mode reconfigurationsystem according to this example embodiment reduces power down to sub-nWrange like DLS logic [1]. Conversely and advantageously, NM mode of thedual-mode reconfiguration system according to this example embodimentavoids the drastic speed (7,755×) and energy (8.2×) degradation of DLS.

Although operation in LSM mode reduces the current drawn by the MCUsystem according to example embodiment to the nA range oncebootstrapped, the DC current absorbed when the harvester voltage isprogressively raised is much larger, as was observed in [1] for DLSlogic. For example, as shown in graphs 600 and 606 in FIG. 6 the current(power) at V_(DD)=0.2V in LSM mode is 17.1× (7.6×) larger than the valueat the minimum-power point V_(DD)=0.45V, because transistors in DLScells are less negatively gate biased at lower V_(DD), and hence draw anexponentially larger current than at the minimum-power point [1]. Thisissue was addressed in [1] by requiring the harvester power to besignificantly raised at power-up, and then allowed to be smaller duringin-field operation. However, this limits the ability of the system toboot up again after a harvesting power outage, as it will not boot untila large harvested power becomes available again.

To solve this issue, a ripple power gating self-startup mechanism isintroduced according to an example embodiment to advantageously allowcold start with limited harvested power. Instead of powering up theentire microcontroller system all at once, the microcontroller system ispartitioned in smaller power domains that are sequentially powered bythe ripple self-startup block 216 (FIG. 2 ), which progressively turnson the relevant header sleep transistors. The gate count in each powerdomain is preferably small enough to keep its power-up peak currentlower than the minimum targeted harvested power, as set by theapplication (e.g., low illuminance in the solar cell 222, FIG. 2 ). Eachripple power gating stage e.g. 700 b in FIG. 7 contains a hysteresisvoltage detector VD1 that turns on the sleep transistor of the nextstage after a delay, in this example a 6-bit programmable delay circuit704 (tunable for testing purposes), when the input voltage into theripple power gating stage e.g. 700 reaches a 250-mV trigger level, inthis example embodiment.

Specifically, in the first ripple power gating stage 700 a, when theharvester voltage V_(SC) detected at VD1 reaches the 250-mV triggerlevel during self-startup, after the programmable delay VD2 is enabled.In turn, VD2 pulls up V_(out,VD2), and as a result, the inverted voltagedetector (IVD) pulls SLEEP 702 a down to turn on the next sleeptransistor, here of the MCU core domain 706. In the next ripple powergating stage 700 b, when the MCU core domain voltage V_(core) detectedat VD1 reaches the 250-mV trigger level during, after the programmabledelay VD2 is enabled. In turn, VD2 pulls up V_(out,VD2), and as aresult, the IVD pulls SLEEP 702 b down to turn on the next sleeptransistor, here of the MEM banks 0&1 708. In the last ripple powergating stage 700 c, when the V_(dm67) voltage detected at VD1 reachesthe 250-mV trigger level during, after the programmable delay VD2 isenabled. In turn, VD2 pulls up V_(out,VD2), and as a result, the IVDpulls SLEEP 702 c down to turn on the next sleep transistor, here of theclock generator 710. It is noted that an instruction memory is not usedin this self-start-up showcase according to an example embodiment, (eventhough it is provided as an extra feature according to exampleembodiments), however ROM (compare 206 in FIG. 2 , containing a bootupprogram) is used.

Graph 800 in FIG. 8 shows the measured waveform of signals e.g. 802 a,802 b, 802 c progressively activating the power domains duringself-startup according to an example embodiment, as powered by anon-chip 0.54 mm² solar cell at 55 lux illuminance (as typical oftwilight). In graph 804, curve 806 shows the current absorbed for aripple start-up (i.e. one domain is turned on and added at a time, withthe previous one being kept on and the next power gated) according tothe example embodiment, powered by the on-chip 0.54 mm² solar cell at 55lux illuminance. Without a conventional “all on” start-up, more than 380lux would be needed for a safe start-up (bright office lighting), asshown in curve 808 in graph 804.

Compared to prior art, embodiments of the present invention provide adual-mode architecture which can improve the minimum energy per gate by5.5× and speed by five orders of magnitude compared with [1], whileachieving an energy/gate that is comparable to [2-3] and lower than[5-6]. In sub-leakage operation, the dual-mode architecture according toan example embodiment can offer >780× improvement in minimum power/gatecompared with [2-6], allowing the system according to an exampleembodiment to fully function at 55 lux light intensity with a 0.54 mm²on-chip solar cell.

FIG. 9 shows a schematic drawing illustrating a cell logic structure 900for a battery-indifferent or purely energy harvested multi-mode system,according to an example embodiment. The cell logic structure 900comprises a CMOS gate circuit 902; a header circuit 904 coupled to theCMOS gate circuit and comprising first and second header transistors906, 908 for coupling in parallel between a supply voltage 909 and theCMOS gate circuit 902; and a footer circuit 910 coupled to the CMOS gatecircuit 902 and comprising first and second footer transistors 912, 914for coupling in parallel between the CMOS gate circuit 902 and a groundvoltage 916; wherein the header and footer circuits 904, 910 areconfigured for switching between different operation modes of themulti-mode system 900, the different operation modes chosen from a rangefrom a normal mode in which feedback paths from an output of the CMOSgate circuit 902 to the gate of the second header transistor 908 and tothe gate of the second footer transistor 914 are substantially or fullydisabled for full swing in the output voltage of the CMOS gate circuit902, and a leakage suppression mode in which the feedback paths aresubstantially or fully enabled.

The first and second header transistors 906, 908 may comprise NMOStransistors.

The first and second footer transistors 912, 914 may comprise PMOStransistors.

The header and footer circuits 904, 910 may be configured for disablingthe feedback by overdriving the gates of the first header transistor 906and the first footer transistor 912.

FIG. 10 shows a schematic diagram illustrating a battery-indifferent orpurely energy harvested multi-mode system 1000, according to an exampleembodiment. The system 1000 comprises an energy harvesting circuit 1002for generating power for the dual mode system; one or more cell logicstructures 900 as described above with reference to FIG. 9 ; and a powermanagement circuit 1006 switching between the different operation modesof the multi-mode system 1000.

The power management circuit 1006 may comprise a self-startup circuitportion 1008 for gradually powering up the multi-mode system 1000 afteran outage of power generated by the harvesting circuit 1002.

The self-startup circuit portion 1008 may be configured to sequentiallypower up partitions of the multi-mode system 1000.

The self-startup circuit portion 1008 may comprise a delay circuit 1010for introducing a delay between power up of the respective partitions.

The dual mode system may further comprise a battery 1004 configured tobe recharged from the harvesting circuit, and the first level of powermay be provided at least partially by the battery 1004, and the secondlevel of power may be provided purely by the harvesting circuit 1002.

The first and second levels of power may be provided purely by differentoutput levels of the harvesting circuit 1002.

FIG. 11 shows a flow chart 1100 illustrating a method of operating acell logic structure for a battery-indifferent or purely energyharvested multi-mode system, according to an example embodiment. At step1102, a header circuit coupled to a CMOS gate circuit is controlled, theheader circuit comprising first and second header transistors forcoupling in parallel between a supply voltage and the CMOS gate circuit,and at step 1104, a footer circuit coupled to the CMOS gate circuit iscontrolled, the footer circuit comprising first and second footertransistors for coupling in parallel between the CMOS gate circuit and aground voltage; such that the multi-mode system is switchable betweendifferent operation modes, the different operation modes chosen from arange from a normal mode in which feedback paths from an output of theCMOS gate circuit to the gate of the second header transistor and to thegate of the second footer transistor are substantially or fully disabledfor full swing in the output voltage of the CMOS gate circuit, and aleakage suppression mode in which the feedback paths are substantiallyor fully enabled.

The first and second header transistors may comprise NMOS transistors.

The first and second footer transistors may comprise PMOS transistors.

The method may comprise controlling the header and footer circuits fordisabling the feedback by overdriving the gates of the first headertransistor and the first footer transistor.

FIG. 12 shows a flowchart 1200 illustrating a method of operatingbattery-indifferent or purely energy harvested multi-mode system,according to an example embodiment. At step 1202, power for the dualmode system is generated using an energy harvesting circuit. At step1204, the method 1100 of operating a cell logic structure is executed.At step 1206, the multi-mode system is switched between the differentoperation modes.

The method may comprise gradually powering up the multi-mode systemafter an outage of power generated by the harvesting circuit.

The method may comprise sequentially powering up partitions of themulti-mode system.

The method may comprise introducing a delay between power up of therespective partitions.

Embodiments of the present invention can have one or more of thefollowing features and associated benefits/advantages:

Feature Benefit/Advantage The ability to support dual- The performanceand energy efficiency are mode operations: normal mode maximized innormal mode, while the and leakage suppression mode power is minimizedin leakage suppression mode (pushed below leakage power) The ability togranularly Graceful energy (speed) and power trade- adjust the starvedcurrent in off can be obtained to adapt to the changes logic gates ofenvironments and requirements The ability to power on each The requiredharvested power for startup is separate power domain greatly reduced,which avoids the need of sequentially during self-startup kick-start asshown in [1]

Embodiments of the present invention can have the followingapplications, by way of example, not limitation:

-   -   provide a solution to operate at both minimum energy mode and        minimum power mode, bridging the gap between battery-powered        systems and purely harvested systems    -   provides to a solution to cold start with limited harvested        power, as opposed to kick-start in [1]

Aspects of the systems and methods described herein may be implementedas functionality programmed into any of a variety of circuitry,including programmable logic devices (PLDs), such as field programmablegate arrays (FPGAs), programmable array logic (PAL) devices,electrically programmable logic and memory devices and standardcell-based devices, as well as application specific integrated circuits(ASICs). Some other possibilities for implementing aspects of the systeminclude: microcontrollers with memory (such as electronically erasableprogrammable read only memory (EEPROM)), embedded microprocessors,firmware, software, etc. Furthermore, aspects of the system may beembodied in microprocessors having software-based circuit emulation,discrete logic (sequential and combinatorial), custom devices, fuzzy(neural) logic, quantum devices, and hybrids of any of the above devicetypes. Of course the underlying device technologies may be provided in avariety of component types, e.g., metal-oxide semiconductor field-effecttransistor (MOSFET) technologies like complementary metal-oxidesemiconductor (CMOS), bipolar technologies like emitter-coupled logic(ECL), polymer technologies (e.g., silicon-conjugated polymer andmetal-conjugated polymer-metal structures), mixed analog and digital,etc.

The above description of illustrated embodiments of the systems andmethods is not intended to be exhaustive or to limit the systems andmethods to the precise forms disclosed. While specific embodiments of,and examples for, the systems components and methods are describedherein for illustrative purposes, various equivalent modifications arepossible within the scope of the systems, components and methods, asthose skilled in the relevant art will recognize. The teachings of thesystems and methods provided herein can be applied to other processingsystems and methods, not only for the systems and methods describedabove.

The elements and acts of the various embodiments described above can becombined to provide further embodiments. These and other changes can bemade to the systems and methods in light of the above detaileddescription.

For example, the self-startup problem addressed by embodiments of thepresent invention also applies to DLS systems such as the DLS systemdescribed in [1]. In general, in the following claims, the terms usedshould not be construed to limit the systems and methods to the specificembodiments disclosed in the specification and the claims, but should beconstrued to include all processing systems that operate under theclaims. Accordingly, the systems and methods are not limited by thedisclosure, but instead the scope of the systems and methods is to bedetermined entirely by the claims.

Also, while in the embodiments described above a battery and a batterycharger are present, the present invention can also be applied to adjustthe frequency-power tradeoff even in systems with only energy harvesting(no battery charge). In such embodiments, one can adapt to verydifferent levels of available/delivered power from the harvester, whichis useful as will be appreciated by a person skilled in the art.

Unless the context clearly requires otherwise, throughout thedescription and the claims, the words “comprise,” “comprising,” and thelike are to be construed in an inclusive sense as opposed to anexclusive or exhaustive sense; that is to say, in a sense of “including,but not limited to.” Words using the singular or plural number alsoinclude the plural or singular number respectively. Additionally, thewords “herein,” “hereunder,” “above,” “below,” and words of similarimport refer to this application as a whole and not to any particularportions of this application. When the word “or” is used in reference toa list of two or more items, that word covers all of the followinginterpretations of the word: any of the items in the list, all of theitems in the list and any combination of the items in the list.

REFERENCES

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The invention claimed is:
 1. A cell logic structure for abattery-indifferent or pure energy harvesting multi-mode system, thecell logic structure comprising: a CMOS gate circuit; a header circuitcoupled to the CMOS gate circuit and comprising first and second headertransistors for coupling in parallel between a supply voltage and theCMOS gate circuit; and a footer circuit coupled to the CMOS gate circuitand comprising first and second footer transistors for coupling inparallel between the CMOS gate circuit and a ground voltage; wherein theheader and footer circuits are configured for switching betweendifferent operation modes of the multi-mode system, the differentoperation modes chosen from a range from a normal mode in which feedbackpaths from an output of the CMOS gate circuit to the gate of the secondheader transistor and to the gate of the second footer transistor aresubstantially or fully disabled for full swing in the output voltage ofthe CMOS gate circuit, and a leakage suppression mode in which thefeedback paths are substantially or fully enabled; and wherein: theheader and footer circuits are configured for disabling the feedback byoverdriving the gates of the first header transistor and the firstfooter transistor.
 2. The cell logic structure of claim 1, wherein: thefirst and second header transistors comprise NMOS transistors and thefirst and second footer transistors comprise PMOS transistor.
 3. Thecell logic structure of claim 1, wherein the first and second headertransistors comprise NMOS transistors.
 4. The cell logic structure ofclaim 1, wherein the first and second footer transistors comprise PMOStransistors.
 5. A method of operating a cell logic structure for abattery-indifferent or pure energy harvesting multi-mode system, themethod comprising the steps of: controlling a header circuit coupled toa CMOS gate circuit, the header circuit comprising first and secondheader transistors for coupling in parallel between a supply voltage andthe CMOS gate circuit, and controlling a footer circuit coupled to theCMOS gate circuit, the footer circuit comprising first and second footertransistors for coupling in parallel between the CMOS gate circuit and aground voltage; such that the multi-mode system is switchable betweendifferent operation modes, the different operation modes chosen from arange from a normal mode in which feedback paths from an output of theCMOS gate circuit to the gate of the second header transistor and to thegate of the second footer transistor are substantially or fully disabledfor full swing in the output voltage of the CMOS gate circuit, and aleakage suppression mode in which the feedback paths are substantiallyor fully enabled; and wherein: the header and footer circuits areconfigured for disabling the feedback by overdriving the gates of thefirst header transistor and the first footer transistor.
 6. The methodof claim 5, wherein: the first and second header transistors compriseNMOS transistors and the first and second footer transistors comprisePMOS transistors.
 7. The method of claim 5, wherein the first and secondheader transistors comprise NMOS transistors.
 8. The method of claim 5,wherein the first and second footer transistors comprise PMOStransistors.